1. Field of the Invention
The present invention relates to video processing. More specifically, it pertains to the minimization of jitter when decoding and presenting a multimedia data stream.
2. Discussion of the Related Art
One feature of many multimedia packages is the ability to receive and decode encoded video and audio data. Under real time operation, information must be decoded and represented on a display, speaker, and/or recording medium (VCR, etc.) at the same rate as it is received. However, as long as the system is not interactive, it can be represented to the viewer at a set reasonable time delay from the time the encoded data is received without the user noticing. The delay, however, must be consistently applied to both the audio and visual data. Therefore, the system must have a clock synchronized to the transmitter clock to ensure that the data is being represented on the display, speakers, and/or recording medium at the same rate as the data was transmitted. The system must also have a clock to ensure that the visual and audio components of the data are synchronized.
The problem of xe2x80x9cjitterxe2x80x9d complicates the synchronization process. Multimedia data representing, for example, a television show has been generated by a variety of recording devices, such as a camera, microphone, computer graphics generator, and so forth. Once the data is generated, an encoder encodes the data in order to reduce the bandwidth required for transmission. The data stream is encoded into a compressed data stream having recognized compression formats such as MPEG1, MPEG2, and so forth.
These data streams include program or system clock references (hereinafter xe2x80x9cPCRxe2x80x9d). These PCR""s are reference points that the encoder inserts to indicate a reference to be used when calculating the time at which the data should be displayed. PCR time markers are placed within the MPEG data stream at, for example, ten per second. Therefore, in an ideal system, one would expect a PCR once every 0.1 seconds.
However, between the encoder and the decoder are a variety of processes that could either speed up or slow down the data rate of the transmitted data stream even though the data rate at the encoder is constant. This effect is referred to herein as xe2x80x9cwanderxe2x80x9d if the variation is slow, and xe2x80x9cjitterxe2x80x9d if the variation is fast. For example, in a transmission involving a satellite link, data must be transmitted through a variety of different levels of atmosphere. The electromagnetic propagation behaves differently through each level of atmosphere causing the data to speed up or slow down. In this and other applications, it is possible that in processing the data stream between encoding and decoding, the data stream is multiplexed and demultiplexed. There is always some synchronization error in demultiplexing elements of a data stream back into that data stream. In general, these effects cause both wander and jitter.
Even with wander and jitter, the average speed at which data arrives over a long period of time is constant. Furthermore, the average rate at which data is consumed must equal the average rate at which the data arrives. However, input wander and jitter means that at any given point, the rate of data in the data stream could either be slightly higher or lower than the average speed. A higher input data rate increases the length of the queue holding the data to be displayed, leading in the worst case to data loss as a result of an overflowed buffer. A lower data rate may lead to the display running out of display data.
To avoid data loss, the receiver clock average frequency must equal the transmitter clock average frequency. However, jitter on the receiver clock can cause noise and color inaccuracy in the video signals displayed on a monitor, and can cause poor signal-to-noise ratios in delta-signal audio digital-to-analog converters (DAC""s). Therefore, to avoid large queues in the receiver, the receiver clock tracks wander and rejects jitter.
One prior art method uses a fixed frequency clock to control the processing of the data stream. This fixed frequency clock does not track the actual input wander and thus the buffers risk overflow as described above. To prevent overflowing the buffers, the system simply removes the data. Instead of depleting the data in the buffers, the system simply withholds displaying any data within the buffers until more data has arrived. However, it is well known how to construct a fixed-frequency oscillator that generates very little jitter.
In a video context, the above prior art method results in occasional repeating or skipping of frames that gives rise to jerky motion in the video sequence. However, in an audio context, audio portions are removed or repeated, resulting in pops and clicks in the audio signals. Therefore, what is desired is a circuit and method for tracking wander without skipping or repeating data to enable smoother presentation of video and a higher fidelity presentation of audio.
FIG. 1 illustrates a prior art circuit for system frequency synthesis in which skipping or repeating data is not necessary. Prior art synthesizer 40 includes a transport demultiplexer 44 receiving a data stream 42 and providing a transport demultiplexer output data stream 46; a processor 48 receiving the transport demultiplexer output data stream 46 and a local timer output signal 62 and providing a processor output signal 50; a digital-to-analog converter (DAC) 52 receiving processor output signal 50 and providing a DAC output signal 54; a voltage control crystal oscillator (VCXO) 56 receiving DAC output signal 54 and providing a VCXO output signal 58; and a local timer 60 receiving VCXO output signal 58 and providing local timer output signal 62.
Processor 48 receives transport demultiplexer output data stream 46""s time marker and a local time when the time marker was received from local timer output signal 62. Processor 48 compares these input signals to determine how much the system clock needs to speed up or slow down to properly synchronize with the transport demultiplexer output data stream 46. Processor 48 outputs an appropriate instruction in processor output signal 50 to DAC 52 where the instruction is converted to a form recognizable by VCXO 56. DAC 52 sends the instruction in DAC output signal 54 to VCXO 56 and VCXO 56 responds by increasing or decreasing the frequency of the clock signals sent over VCXO output signal 58 to local timer 60, thus completing the loop.
This configuration suffers from several disadvantages. First, VCXO 56 generates more jitter than fixed-frequency oscillators. Second, VCXO 56 is very difficult to Control. There are non-linearities within both DAC 52 and VCXO 56 thereby limiting the ability to adjust local timer 60 in response to jitter detected within transport demultiplexer 44. Third, the system provides for little attenuation of jitter introduced within the local control system. Fourth, VCXO 56 requires that the capacitance across a crystal be changed in response to a control signal, which makes them expensive to implement on a single integrated circuit. Therefore, what is desired is a circuit and method for synchronizing a local clock to a data stream to improve synchronization control and jitter attenuation.
The present invention provides a circuit and method for synchronizing a local clock to a data stream to compensate for input jitter and limit internally generated jitter. A synchronization circuit has a numerically controlled oscillator (NCO). The NCO has an accumulator and receives two input values, a number and a feedback value fed back from the output of the accumulator. Thus, the accumulator is configured to repeatedly add the number to the feedback value and output the result as an accumulator output with each clock cycle. The synchronization circuit includes a phase-locked loop (PLL), which receives the output value of the accumulator and attenuates high frequency jitter. The number made available to the accumulator is selected so as to maximize the jitter frequency of the accumulator output. As a low pass filter, the PLL filters out the high frequency jitter.
A method for synchronizing is also provided. The method increments a first variable by a second variable resulting in a sum. A most significant bit of the remainder of the sum when divided by a maximum value is output to a phase-locked loop.
The principles of the present invention will best be understood in accordance with the following detailed description and in accordance with the claims.